Developing a symbolic simulator for VHDL for use in verifying hierarchical hardware systems (R)

By: Vaidya, NachiketContributor(s): Chakraborty, SupratikLanguage: English Series: Publication details: Mumbai ; IIT ; 2008Edition: Description: iii,63 p; 30 cmISBN: Subject(s): Chakraborty, Supratik | Theses and Dissertations | Computer architecture , VHDL(Computer hardware description language) , Computer input-output equipment
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Item type Current library Call number Status Notes Date due Barcode Item holds
Theses and Dissertations Theses and Dissertations Central Library, IITB
043:681.3.07Vai Not for loan D02B24 217576
Total holds: 0

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