Developing a symbolic simulator for VHDL for use in verifying hierarchical hardware systems (R)
Vaidya, Nachiket
Developing a symbolic simulator for VHDL for use in verifying hierarchical hardware systems (R) - - Mumbai IIT 2008 - iii,63 p. 30 cm - .
Chakraborty, Supratik
Theses and Dissertations
Computer architecture , VHDL(Computer hardware description language) , Computer input-output equipment
043:681.3.07Vai
Developing a symbolic simulator for VHDL for use in verifying hierarchical hardware systems (R) - - Mumbai IIT 2008 - iii,63 p. 30 cm - .
Chakraborty, Supratik
Theses and Dissertations
Computer architecture , VHDL(Computer hardware description language) , Computer input-output equipment
043:681.3.07Vai