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Look-up table approach for accurate simulation of deep submicron MOS circuits (R) by Dasarapu, Vinay Kumar [Author] | Patil, Mahesh B [Supervisor] | Rao, Ramgopal V [Supervisor] | Indian Institute of Technology Bombay Department of Electrical Engineering. Language: English Publication details: Bombay IIT 2005Dissertation note: Thesis Ph.D Indian Institute of Technology Bombay. Department of Electrical Engineering 2005 Availability: Items available for reference: Not for loan (1) Call number: 043:621.372:621.382.3 Das.
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Optimization of deep sub-micron CMOS technologies for mixed signal circuits (R) by Narasimhulu, K [Author] | Rao Ramgopal, V [Supervisor] | Indian Institute of Technology Bombay Department of Electrical Engineering. Language: English Publication details: Bombay IIT 2006Dissertation note: Thesis Ph.D Indian Institute of Technology Bombay. Department of Electrical Engineering 2006 Availability: Items available for reference: Not for loan (1) Call number: 043:621.382.3 Nar.
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Bottom-up approaches for nano-scale CMOS scaling (R) by Roy, Urmimala [Author] | Rao, Ramgopal V [Supervisor] | Indian Institute of Technology Bombay. Department of Electrical Engineering. Language: English Publication details: Mumbai IIT 2009Dissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2011 Availability: Items available for reference: Not for loan (2) Call number: 043:621.382:620.168.3 Kha, ...
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I/O and ESD device optimization for nanometer node CMOS technologies (R) by Shrivastava, Mayank [Author] | Rao, Ramgopal V [Supervisor] | Baghini, M.S [Supervisor]. Language: English Publication details: Mumbai IIT 2010Dissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2010 Availability: Items available for reference: Not for loan (1) Call number: 043:621.382:621.372 Shr.
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