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Behavioral fault simulation for ideal (R) by Venkateswaran, R | Venkatesh, G. and Sherlekar, S.D. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1992Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06Ven.
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Parallel logic simulation (R) by Khare, A.N | Sherlekar, S.D. and Venkatesh, G. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1992Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06:681.327.8Kha.
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Design of monitored self-checking sequential circuits (R) by Parekhji, Rubin A [Author] | Venkatesh, G [Supervisor] | Sherlekar, S.D [Supervisor] | Indian Institute of Technology Bombay. Department of Computer Science and Engineering. Language: English Publication details: Bombay IIT 1994Dissertation note: Thesis
Ph.D.
Indian Institute of Technology Bombay. Department of Computer Science and Engineering 1994 Availability: Items available for reference: Not for loan (1) Call number: 043:681.3:658.562 Par.
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High level synthesis of DSP algorithms (R) by Mehendale, Mahesh M [Author] | Sohoni, Milind [Supervisor] | Sherlekar, S.D [Supervisor] | Indian Institute of Technology Bombay. Department of Computer Science and Engineering. Language: English Publication details: Mumbai IIT 1999Dissertation note: Thesis
Ph.D.
Indian Institute of Technology Bombay. Department of Computer Science and Engineering 1999 Availability: Items available for reference: Not for loan (1) Call number: 043:621.385.832:681.3 Meh.
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Optimizing Fortran compiler : part III (R) by Sherlekar, S.D | Dhamdhere, D. M. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1982Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06:519.3She.
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