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		No cover image available Fully testable circuit synthesis for delay and multiple stuck-at faults (R) by Shah, Toral Ankur [Author] \| Singh, Virendra [Supervisor] \| Indian Institute of Technology Bombay. Department of Electrical Engineering. Material type: Text; Format: print ; Literary form: Not fiction Language: English Publication details: Mumbai IIT 2018Dissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2018 Availability: Items available for reference: Not for loan (1) Call number: 043:621.372:621.382 Sin. Lists: Display List 08/10/2018-14/10/2018. Add to cart (remove)
		Power system analysis : a dynamic perspective by Shubhanga, K.N. Language: English Publication details: Pearson Education 2018Availability: Items available for loan: 1 Call number: 621.315 Shu. Lists: Display List 10/12/2018-16/12/2018. Place hold Add to cart (remove)
		Network Analysis by Van Valkenburg, M.E. Edition: 3rd ed.Material type: Text; Format: print ; Literary form: Not fiction Language: English Publication details: New Delhi PHI Learning 2012Availability: Not available: Checked out (1). Lists: Display List 25/11/2019 - 01/12/2019. Place hold Add to cart (remove)

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