Fully testable circuit synthesis for delay and multiple stuck-at faults (R)
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
Item type | Current library | Call number | Status | Notes | Date due | Barcode | Item holds |
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Central Library, IITB Pamphlet Section (Theses, Standards, Reports) | 043:621.372:621.382 Sin | Not for loan | D03A24 | 242946 |
Total holds: 0
Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2018
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