Fully testable circuit synthesis for delay and multiple stuck-at faults (R)
Material type:
TextLanguage: English Publication details: Mumbai IIT 2018Description: xvii,101 p. 30 cmSubject(s): Theses and Dissertations | Delay faults(Semiconductors) | Electric circuit analysis | Electric circuits | Integrated circuits -- Very large scale integration -- TestingDissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2018
| Item type | Current library | Call number | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|
Theses and Dissertations
|
Central Library, IITB Pamphlet Section (Theses, Standards, Reports) | 043:621.372:621.382 Sin | Not for loan | D03A24 | 242946 |
Total holds: 0
Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2018
There are no comments on this title.