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		No cover image available Boolean function minimization (R) by Hayatnagarkar, N.K \| Bhujade, M.R. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1984Availability: Items available for reference: Not for loan (1) Call number: 043:621.374.32:681.3Hay. Add to cart (remove)
		No cover image available Simulation of radiation effects in CMOS combinational logic circuits (R) by Sharma, Chander Vinit \| Das, A. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1994Availability: Items available for reference: Not for loan (1) Call number: 043:621.372:621.382:539.16Sha. Add to cart (remove)
		No cover image available Combinatorial optimization in VLSI systems : state assignment in logic circuits (R) by Gupta, B.N.V.M \| Narayanan, H. and Desai, M.P. Series: Edition: Language: English Publication details: Mumbai ; IIT ; 1998Availability: Items available for reference: Not for loan (1) Call number: 043:621.372:621.382:519.3Gup. Add to cart (remove)
		No cover image available Parallel simulation of verilog HDL designs (R) by Akarsh Kumar \| Patkar, Sachin B. Series: Edition: Language: English Publication details: Mumbai ; IIT ; 2013Availability: Items available for reference: Not for loan (1) Call number: 043:621.374.32:681.3Aka. Add to cart (remove)
		No cover image available Some results on complexity of boolean functions (R) by Ramarao, V \| Kekre, H.B. and Sahasrabudhe, S.C. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1981Availability: Items available for reference: Not for loan (1) Call number: 043:621.374.32:681.3Ram. Add to cart (remove)
		No cover image available On the likelihood of multiple errors in logic circuits due to neutron strikes : a circuit and layout perspective (R) by Nanditha Rao, P [Author] \| Desai, Madhav P [Supervisor] \| Indian Institute of Technology Bombay. Department of Electrical Engineering. Language: English Publication details: Mumbai IIT 2017Dissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2017 Availability: Items available for reference: Not for loan (1) Call number: 043:621.382.3 Nan. Add to cart (remove)
		Digital design with an introduction to the verilog HDL by Mano, M. Moris [Author] \| Ciletti, Michael D [Author]. Edition: 5th edMaterial type: Text; Format: print ; Literary form: Not fiction Language: English Publication details: Chennai Pearson Education 2013Availability: Not available: Checked out (1). Place hold Add to cart (remove)
		Digital design : with an introduction to the Verilog HDL, VHDL, and SystemVerilog by Mano, M. Morris [Author] \| Ciletti, Michael D [Author]. Edition: 6th ed.Material type: Text; Format: print ; Literary form: Not fiction Language: English Publication details: Nodia Pearson India Education Service 2019Availability: Items available for loan: 1 Call number: 681.3(VHDL) Man(2). Lists: New Arrivals : Display Books List from 13/05/2024-19/05/2024. Place hold Add to cart (remove)

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