On the likelihood of multiple errors in logic circuits due to neutron strikes : a circuit and layout perspective (R)
Language: English Publication details: Mumbai IIT 2017Description: vi,96 p. 30 cmSubject(s): Theses and Dissertations | Electronic circuits | Metal oxide semiconductor field-effect transistors -- effect transistors | Digital electronics | Logic circuitsDissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 2017Item type | Current library | Call number | Status | Notes | Date due | Barcode | Item holds |
---|---|---|---|---|---|---|---|
Theses and Dissertations | Central Library, IITB Pamphlet Section (Theses, Standards, Reports) | 043:621.382.3 Nan | Not for loan | D08A20 | 241386 |
Total holds: 0
Thesis
Ph.D.
Indian Institute of Technology Bombay. Department of Electrical Engineering 2017
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