Scaling and optimization of CMOS technologies for logic and non-volatile memory applications (R)

By: Mohapatra, Nihar Ranjan [Author]Contributor(s): Ramgopal Rao, V [Supervisor] | Desai, Madhav P [Supervisor] | Indian Institute of Technology Bombay. Department of Electrical EngineeringLanguage: English Publication details: Bombay IIT 2003Description: xii,110 p; 30 cmSubject(s): Ramgopal Rao, V. and Desai, Madhav P | Theses and Dissertations | Metal oxide semiconductors | Complimentary | Memory devicesDissertation note: Thesis Ph.D Indian Institute of Technology Bombay. Department of Electrical Engineering 2003
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Holdings
Item type Current library Call number Status Notes Date due Barcode Item holds
Theses and Dissertations Theses and Dissertations Central Library, IITB
Pamphlet Section (Theses, Standards, Reports)
043:621.372:621.382 Moh Not for loan D08A26 201473
Total holds: 0

Thesis Ph.D Indian Institute of Technology Bombay. Department of Electrical Engineering 2003

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