Security and testability issues in modern VLSI chips (R) (Record no. 275982)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01019nam a22002537a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20230603115541.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190717b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | IITB |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | eng |
| 080 ## - UNIVERSAL DECIMAL CLASSIFICATION NUMBER | |
| Universal Decimal Classification number | 043:621.372:621.382 |
| Item number | Ahl |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Ahlawat, Satyadev |
| 9 (RLIN) | 9727 |
| Relator term | Author |
| 245 ## - TITLE STATEMENT | |
| Title | Security and testability issues in modern VLSI chips (R) |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Mumbai |
| Name of publisher, distributor, etc. | IIT |
| Date of publication, distribution, etc. | 2018 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xvi,226 p. |
| Dimensions | 30 cm |
| 502 ## - DISSERTATION NOTE | |
| Dissertation note | Thesis |
| Degree type | Ph.D. |
| Name of granting institution | Indian Institute of Technology Bombay. Department of Electrical Engineering |
| Year degree granted | 2018 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Theses and Dissertations |
| 9 (RLIN) | 21 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digital integrated circuits |
| General subdivision | Design and construction |
| -- | Data processing |
| 9 (RLIN) | 9749 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Integrated circuits |
| General subdivision | Very largescale integration |
| -- | Testing |
| 9 (RLIN) | 9750 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Integrated circuits |
| General subdivision | Very largescale integration |
| -- | Security measures |
| 9 (RLIN) | 9751 |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Singh, Virendra |
| Relator term | Supervisor |
| 9 (RLIN) | 2135 |
| 710 ## - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | Indian Institute of Technology Bombay. |
| Subordinate unit | Department of Electrical Engineering |
| 9 (RLIN) | 64 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Theses and Dissertations |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Full call number | Barcode | Date last seen | Price effective from | Koha item type | Public note |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, IITB | Central Library, IITB | Pamphlet Section (Theses, Standards, Reports) | 17/07/2019 | 043:621.372:621.382 Ahl | 245315 | 17/07/2019 | 17/07/2019 | Theses and Dissertations | D03A23 |