Modeling accelerated logic simulation on networks-on-chip using systemC (R)
Jaroli, Samyak
Modeling accelerated logic simulation on networks-on-chip using systemC (R) - - Mumbai IIT 2013 - ix,89 p. 30 cm - .
Patkar, Sachin B.
Theses and Dissertations
Networks on a chip , Systems on a chip , C++(Computer program language)
043:621.372:621.382Jar
Modeling accelerated logic simulation on networks-on-chip using systemC (R) - - Mumbai IIT 2013 - ix,89 p. 30 cm - .
Patkar, Sachin B.
Theses and Dissertations
Networks on a chip , Systems on a chip , C++(Computer program language)
043:621.372:621.382Jar