Simulation of latch-up in CMOS technology (R)
Mehrotra, Samit S.
Simulation of latch-up in CMOS technology (R) - - Mumbai IIT 2002 - xiii,91 p. 30 cm - .
Vasi, Juzer M. and Patil, Mahesh B.
Theses and Dissertations
Metal oxide semiconductors , Complementary-Simulation methods
043:621.382:681.3Meh
Simulation of latch-up in CMOS technology (R) - - Mumbai IIT 2002 - xiii,91 p. 30 cm - .
Vasi, Juzer M. and Patil, Mahesh B.
Theses and Dissertations
Metal oxide semiconductors , Complementary-Simulation methods
043:621.382:681.3Meh