| 000 | 00892nam a2200253Ia 4500 | ||
|---|---|---|---|
| 003 | OSt | ||
| 005 | 20221206162905.0 | ||
| 008 | 211118s9999 xx 000 0 und d | ||
| 020 | _a978-1-59829-754-6 | ||
| 040 | _cIITB | ||
| 041 | _aeng | ||
| 100 |
_aBalasubramonian, Rajeev _922090 _eAuthor |
||
| 245 | 0 | _aMulti-core cache hierarchies (e-book) | |
| 260 |
_aSan Rafael _bMorgan and Claypool / _bIEEE Press / _bSpringer _c2011 |
||
| 440 |
_aSynthesis lectures on computer architecture _921153 |
||
| 500 | _aIEEE Morgan and Claypool Computer and Information Science (CIS) collection | ||
| 650 | 0 |
_923361 _aCache memory |
|
| 650 | 0 |
_94861 _aComputer architecture |
|
| 650 |
_aMulti-core processors _923907 |
||
| 700 |
_aJouppi, Norman P. _eAuthor _922091 |
||
| 700 |
_aMuralimanohar, Naveen _eAuthor _922092 |
||
| 856 | _uhttps://ieeexplore.ieee.org/document/6812718 | ||
| 942 |
_cEB _2udc |
||
| 999 |
_c278391 _d278391 |
||