| 000 | 01063nam a2200301Ia 4500 | ||
|---|---|---|---|
| 003 | OSt | ||
| 005 | 20240821172159.0 | ||
| 008 | 211118s9999 xx 000 0 und d | ||
| 020 | _a978-1-60845-236-1 | ||
| 040 | _cIITB | ||
| 041 | _aeng | ||
| 100 |
_aHarris, Tim _eEditor _921976 |
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| 245 | 0 | _aTransactional memory (e-book) | |
| 250 | _a2nd ed | ||
| 260 |
_aSan Rafael _bMorgan and Claypool / _bIEEE Press / _bSpringer _c2010 |
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| 440 |
_aSynthesis lectures on computer architecture _921153 |
||
| 500 | _aIEEE Morgan and Claypool Computer and Information Science (CIS) collection | ||
| 650 | 0 |
_aParallel programming (Computer science) _vCongresses _91865 |
|
| 650 | 0 |
_923275 _aSynchronization |
|
| 650 | 0 |
_923274 _aThreads (Computer programs) |
|
| 650 | 0 |
_923276 _aTransaction systems (Computer systems) |
|
| 650 | 0 |
_94861 _aComputer architecture |
|
| 650 |
_aCache coherenc _923570 |
||
| 700 |
_aLarus, James _eAuthor _921977 |
||
| 700 |
_aRajwar, Ravi _eAuthor _921864 |
||
| 856 | _uhttps://ieeexplore.ieee.org/document/6813393 | ||
| 942 |
_cEB _2udc |
||
| 999 |
_c278331 _d278331 |
||