| 000 | 00706 a2200265 4500 | ||
|---|---|---|---|
| 001 | 302820 | ||
| 020 | _a | ||
| 041 | _aeng | ||
| 080 | _a043:621.374.32:681.3Rat | ||
| 245 | _aCompiler based analysis of verilog HDL based digital design and its application to VLSI CAD (R) | ||
| 250 | _a | ||
| 260 | _aMumbai | ||
| 260 | _bIIT | ||
| 260 | _c2011 | ||
| 300 | _av,53 p. | ||
| 300 | _c30 cm | ||
| 490 | _a | ||
| 100 | _aRathi, Aayush | ||
| 700 | _aPatkar, Sachin | ||
| 650 | _aPatkar, Sachin | ||
| 650 | _aTheses and Dissertations | ||
| 650 | _aCompute-aided design , Integrated circuits-Very large scale integration , Verilog(Computer hardware description language) | ||
| 942 | _cTD | ||
| 942 | _2UDC | ||
| 999 |
_c215774 _d215774 |
||