| 000 | 00643 a2200265 4500 | ||
|---|---|---|---|
| 001 | 293562 | ||
| 020 | _a | ||
| 041 | _aeng | ||
| 080 | _a043:621.382:681.3Meh | ||
| 245 | _aSimulation of latch-up in CMOS technology (R) | ||
| 250 | _a | ||
| 260 | _aMumbai | ||
| 260 | _bIIT | ||
| 260 | _c2002 | ||
| 300 | _axiii,91 p. | ||
| 300 | _c30 cm | ||
| 490 | _a | ||
| 100 | _aMehrotra, Samit S. | ||
| 700 | _aVasi, Juzer M. and Patil, Mahesh B. | ||
| 650 | _aVasi, Juzer M. and Patil, Mahesh B. | ||
| 650 | _aTheses and Dissertations | ||
| 650 | _aMetal oxide semiconductors , Complementary-Simulation methods | ||
| 942 | _cTD | ||
| 942 | _2UDC | ||
| 999 |
_c209394 _d209393 |
||