| 000 | 00698 a2200265 4500 | ||
|---|---|---|---|
| 001 | 245658 | ||
| 020 | _a | ||
| 041 | _aeng | ||
| 080 | _a043:681.3.07Vai | ||
| 245 | _aDeveloping a symbolic simulator for VHDL for use in verifying hierarchical hardware systems (R) | ||
| 250 | _a | ||
| 260 | _aMumbai | ||
| 260 | _bIIT | ||
| 260 | _c2008 | ||
| 300 | _aiii,63 p. | ||
| 300 | _c30 cm | ||
| 490 | _a | ||
| 100 | _aVaidya, Nachiket | ||
| 700 | _aChakraborty, Supratik | ||
| 650 | _aChakraborty, Supratik | ||
| 650 | _aTheses and Dissertations | ||
| 650 | _aComputer architecture , VHDL(Computer hardware description language) , Computer input-output equipment | ||
| 942 | _cTD | ||
| 942 | _2UDC | ||
| 999 |
_c201012 _d201012 |
||