| 000 | 00696 a2200289 4500 | ||
|---|---|---|---|
| 001 | 59159 | ||
| 020 | _a0 | ||
| 041 | _aeng | ||
| 080 | _a043:681.3.06Ana | ||
| 245 | _aIdeal to VHDL translator (R) | ||
| 250 | _a | ||
| 260 | _aBombay | ||
| 260 | _bIIT | ||
| 260 | _c1991 | ||
| 300 | _a85 p. | ||
| 300 | _c28 cm | ||
| 490 | _a | ||
| 100 | _aAnand, K. | ||
| 700 | _aSherlekar, S.D. and Verma, A.K. | ||
| 650 | _aSherlekar, S.D. and Verma, A.K. | ||
| 650 | _aTheses and Dissertations | ||
| 650 | _aIDEAL (Integrated Design Automation Language) | ||
| 650 | _aVHDL (VHSIC Hardware Description Language) | ||
| 650 | _aComputer hardware descriptionlanguage | ||
| 942 | _cTD | ||
| 942 | _2UDC | ||
| 999 |
_c170839 _d170839 |
||