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		No cover image available Timing analysis and optimization of sequential circuits by Maheshwari, Naresh \| Sapatnekar, Sachin S \| . Series: Edition: Language: English Publication details: ; Boston : Kluwer Academic Pub., 1999 ; 1999Availability: Items available for loan: 1 Call number: 621.374.32:681.3 Mah. Place hold Add to cart (remove)
		Fault diagnosis of analog integrated circuits by Kabisatpathy, Prithviraj \| Barua, Alok \| Sinha, Satyabroto \| . Series: Edition: Language: English Publication details: A.A. Dordrecht ; Springer ; 2005Availability: Items available for loan: 1 Call number: 621.372:621.382Kab. Place hold Add to cart (remove)
		Digital VLSI systems design : a design manual for implementation of projects on FPGAs and ASICs using verilog by Ramachandran, S \| . Series: Edition: Language: English Publication details: Dordrecht ; Springer ; 2007Availability: Items available for loan: 1 Call number: 621.374.32:681.3Ram. Place hold Add to cart (remove)
		Computer aided verification : 26th international conference, CAV, held as part of the vienna summer of logic, VSL, Vienna, Austria, July 18-22, 2014 (e-book) by . Series: Lecture notes in computer science ; v.8559Edition: Language: English Publication details: Berlin ; Springer ; 2014Online access: Click here to access online Availability: Items available for reference: Not for loan (1) . Add to cart (remove)
		No cover image available Hardware verification using inductive theorem proving (R) by Agrawal, Vatsalya \| Sivakumar, G. Series: Edition: Language: English Publication details: Mumbai ; IIT ; 2005Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.07:517.1Agr. Add to cart (remove)
		No cover image available Equational theorem proving methods for hardware verification (R) by Gopale, Shyamsunder R \| Sivakumar, G. Series: Edition: Language: English Publication details: Mumbai ; IIT ; 1999Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.07:517.1Gop. Add to cart (remove)
		No cover image available Timing verification of VLSI digital design (R) by Bhagwat, Borole Pramod \| Desai, M.P. Series: Edition: Language: English Publication details: Mumbai ; IIT ; 1998Availability: Items available for reference: Not for loan (1) Call number: 043:621.374.32:681.3Bha. Add to cart (remove)

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