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		No cover image available Topological optimisation of PLAs using folding (R) by Kane, S.K \| Vasi, J.M. and Sherlekar, S.D. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1985Availability: Items available for reference: Not for loan (1) Call number: 043:621.374.32:681.3Kan. Add to cart (remove)
		No cover image available Design and implementation of modula-2 computer on MC68000 system (R) by Karmarkar, S.K \| Sherlekar, S.D. and Biswas, S. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1986Availability: Items available for reference: Not for loan (1) Call number: 043:681.326.32:681.3.06Kar. Add to cart (remove)
		No cover image available Studies in testing of transistor stuck-open faults in combinational CMOS circuits (R) by Sherlekar S.D [Author] \| Vasi, J [Supervisor] \| Indian Institute of Technology Bombay. Department of Electrical Engineering. Language: English Publication details: Bombay IIT 1987Dissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Electrical Engineering 1987 Availability: Items available for reference: Not for loan (1) Call number: 043:621.372:621.382 She. Add to cart (remove)
		No cover image available High level synthesis using ideal (R) by Urdhwareshe, Nachiket \| Venkatesh, G. and Sherlekar, S.D. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1991Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06Urd. Add to cart (remove)
		No cover image available Ideal to VHDL translator (R) by Anand, K \| Sherlekar, S.D. and Verma, A.K. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1991Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06Ana. Add to cart (remove)
		No cover image available Development of input interface for IDEAL (R) by Venkateswarlu, M \| Sherlekar, S.D. and Verma, A.K. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1992Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06:658.562Ven. Add to cart (remove)
		No cover image available Methodologies for the design of self-checking circuits (R) by Pagey, Sandeep [Author] \| Sherlekar, S.D [Supervisor] \| Venkatesh, G [Supervisor] \| Indian Institute of Technology Bombay. Department of Computer Science and Engineering. Language: English Publication details: Bombay IIT 1993Dissertation note: Thesis Ph.D. Indian Institute of Technology Bombay. Department of Computer Science and Engineering 1993 Availability: Items available for reference: Not for loan (1) Call number: 043:681.3:658.562 Pag. Add to cart (remove)
		No cover image available Formal semantics of broadcasting sequential processes (R) by Goregaokar, S.R \| Sherlekar, S.D. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1985Availability: Items available for reference: Not for loan (1) Call number: 043:681.3.06:621.391Gor. Add to cart (remove)
		No cover image available Improved decision procedures for propositional temporal logic for timing verification of digital systems (R) by Bapat, S \| sherlekar, S.D. Series: Edition: Language: English Publication details: Bombay ; IIT ; 1986Availability: Items available for reference: Not for loan (1) Call number: 043:621.391.8:681.3:16Bap. Add to cart (remove)

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