FPGA based design of memory management unit (R)

By: Rajadnya, Samir GContributor(s): Sahasrabudhe, S.C. and Rao, S.S.S.PLanguage: English Series: Publication details: Bombay ; IIT ; 1995Edition: Description: 118 p; 28 cmISBN: Subject(s): Sahasrabudhe, S.C. and Rao, S.S.S.P | Theses and Dissertations | Field programmable gate arrays , Memory management(Computer science)
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Holdings
Item type Current library Call number Status Notes Date due Barcode Item holds
Theses and Dissertations Theses and Dissertations Central Library, IITB
043:621.374.32:681.3.07Raj Not for loan D03B06 175809
Total holds: 0

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