Compiler based analysis of verilog HDL based digital design and its application to VLSI CAD (R)
Rathi, Aayush
Compiler based analysis of verilog HDL based digital design and its application to VLSI CAD (R) - - Mumbai IIT 2011 - v,53 p. 30 cm - .
Patkar, Sachin
Theses and Dissertations
Compute-aided design , Integrated circuits-Very large scale integration , Verilog(Computer hardware description language)
043:621.374.32:681.3Rat
Compiler based analysis of verilog HDL based digital design and its application to VLSI CAD (R) - - Mumbai IIT 2011 - v,53 p. 30 cm - .
Patkar, Sachin
Theses and Dissertations
Compute-aided design , Integrated circuits-Very large scale integration , Verilog(Computer hardware description language)
043:621.374.32:681.3Rat